User contributions for Alexander

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14 April 2024

6 February 2024

5 February 2024

2 February 2024

30 January 2024

29 January 2024

15 January 2024

14 January 2024

  • 22:2822:28, 14 January 2024 diff hist +349 m X86 microarchitecture levelsClarification about feature support with x87 and MMX current
  • 22:2322:23, 14 January 2024 diff hist +1,233 N X86 microarchitecture levelsCreated page with "{{DISPLAYTITLE:x86 microarchitecture levels}} These are the '''microarchitecture levels''' designated by Alexander Nicholi for the 16- and 32-bit {{wp|x86}} microarchitecture. It was initially authored as part of the Sirius DOS project as an ABI concept, but is now a concept related to the {{wp|x86-64#Microarchitecture_levels|x86-64 microarchitecture levels}} jointly defined by Intel, AMD, Red Hat and SUSE. ==x86-v1== Original 8086 instruction set..."

12 January 2024

  • 01:1801:18, 12 January 2024 diff hist +7,465 N Protocol SevenCreated page with "'''Internet Protocol version 7''', often shortened to '''Protocol Seven''' or '''IPv7''', is the name of a new version of the {{wp|Internet Protocol}} created under the umbrella of the Wired {{expl|INFRACOM|Infrastructure Commission}}. It is designed as a system of extensions to the dominant {{wp|IPv4}} protocol in use on the Web today. ==Purpose== ===Failure of IPv6=== The contemporary Worldwide Web was originally brought to the public in the form of IPv4. When certain..." current
  • 01:1201:12, 12 January 2024 diff hist +5,952 N Internetworked binaryCreated page with "The '''internetworked binary''', shortened and stylised to '''''ib''''', is a network protocol operating on TCP and UDP. It is often called the ''master protocol'', as it provides the framing for six different subprotocols modelled for different approaches of information sharing. ==Background== There are many thousands of different layer 7 protocols built atop both TCP and UDP. Due to the incidence of contrast between the IETF's four-layer IP suite and the now-ubiquitou..." current
  • 01:1201:12, 12 January 2024 diff hist 0 N Category:ProtocolsCreated blank page current
  • 01:1101:11, 12 January 2024 diff hist +79,313 N SimbaCreated page with "'''Simba''' is the codename for an Epiphany-like processor designed for multicore GPGPU. ==Technical overview== The Simba processor is designed with 256 compute cores. Each core will have 256 KiB of IVRAM for a total of 64 MiB of fast, core-local memory. There will also be at least 64 MiB of slower, on-board EVRAM which is shareable between cores and the CPU. ===IVRAM instead of cache=== Each core's IVRAM is only accessible by the core that is paired to it. Dedicated D..." current
  • 01:0401:04, 12 January 2024 diff hist 0 N Category:Hardware designCreated blank page current
  • 01:0001:00, 12 January 2024 diff hist +749 N Template:Infobox ibCreated page with "{| style="border-radius:0.5rem;border:0.2em solid rgba(88,88,88,0.6);background-color:rgba(88,88,88,0.05);padding-top:5pt" width="300px" align="right" |- ! colspan="4" width="100%" style="font-size:175%" | {{{1|''ib''}}}<br/> 280px |- | colspan="4" width="100%" | <ol style="list-style-type:upper-roman;display:block;margin-left:auto;margin-right:auto;width:fit-content"> <li>Persistent Transmission</li> <li>ib-TTP|Transactional Transmissio..."

10 January 2024

8 January 2024

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