x86 microarchitecture levels

From XionKB
Revision as of 22:23, 14 January 2024 by Alexander (talk | contribs) (Created page with "{{DISPLAYTITLE:x86 microarchitecture levels}} These are the '''microarchitecture levels''' designated by Alexander Nicholi for the 16- and 32-bit {{wp|x86}} microarchitecture. It was initially authored as part of the Sirius DOS project as an ABI concept, but is now a concept related to the {{wp|x86-64#Microarchitecture_levels|x86-64 microarchitecture levels}} jointly defined by Intel, AMD, Red Hat and SUSE. ==x86-v1== Original 8086 instruction set...")
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)
Jump to navigationJump to search

These are the microarchitecture levels designated by Alexander Nicholi for the 16- and 32-bit x86 microarchitecture. It was initially authored as part of the Sirius DOS project as an ABI concept, but is now a concept related to the x86-64 microarchitecture levels jointly defined by Intel, AMD, Red Hat and SUSE.

x86-v1

Original 8086 instruction set. Supported by all x86 microprocessors. Does not include x87 floating-point coprocessor instructions or any variety of SIMD (e.g. MMX and SSE).

x86-v2

Minimum feature set is that of the 80286. Supports protected mode and x87 floating-point instructions.

x86-v3

Minimum feature set is that of the i486. Supports all of the 32-bit extensions from the i386, protected mode, and x87 floating-point. Does not include any variety of SIMD (e.g. MMX, SSE, and 3DNow!).

x86-v4

Minimum feature set is that of the Pentium, plus CPUID and MMX instructions. Supports protected mode and x87 floating-point instructions. Does not include SSE, 3DNow!, or any further P5/P6-era instructions (such as SYSENTER).